The core of the whole amplifier circuit is the TAS5630B one connection is based on modified the recommended BTL mode stereo input, which is listed by the manufacturer in Selection of the final chip involvement consisted of four different...Electronics Projects, TAS5630B 300W Class D Amplifier Circuit "audio amplifier circuits, audio control circuits, class d amplifier circuit, ic amplifier, " Date 2019/08/04
The core of the whole amplifier circuit is the TAS5630B one connection is based on modified the recommended BTL mode stereo input, which is listed by the manufacturer in Selection of the final chip involvement consisted of four different modes, of the optional input pins M1 to M3:
TAS5630B 2 x BTL – two separate channels (full bridge connection, power up to 2x300W) TAS5630B 1 x PBTL – the only channel in bridging (parallel output up to 1x400W) TAS5630B 4 x – four separate channels (performance 4x145W to 2? Or 4x75W into 4?) TAS5630B 1 x BTL + 2 x SE – two channels involved in half the bridge (SE) and one channel to full bridge (BTL), suitable, for example, for 2.1 speakers. Selected was mode 2 x BTL, I mean the classic stereo modes,
TAS5630B from which it can be seen that the input the signal is transferred to the pins of INPUT_A to D, which then goes into the filter slucky. In this block processes the input signal together with the signal from the feedback then progressing through the analog multiplexer to the analog comparator, where PWM modulation occurs by comparing the input signal and the signal from the oscillator, which is known from the theory of the D-class block of the PWM receiver Process the PWM signal and oversees its parameters through the feedback of the slug through the detector the activities of PWM.
Block TAS5630B protection circuit supervises the block management on the end transistors that it is possible to disconnect the short circuiting or crossing the temperature of the chip. The following block management is the timing, which is responsible for the correct timing and switching for terminal transistors and thus can not occur to the current opening in the counter phase (the so-called “dead time”). For this block, followed by the actual drive, powered from pins GVDD_A to D and behind them are the power terminal transistors, which power supply is transferred through the pins PVDD_A to D. The outputs of the end transistors are then out to the pins of OUT_A to D.