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PIC24FJ16GA002 parallel processing computer

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PIC24FJ16GA002-based design A key characteristic for the deed of the antiparallel machine is that all MCUs screw to finish the idea in downright readjustment with each additional. This is achieved by using a vernacular foreign clock for all the MCUs, and by forcing all MCUs to solon action at the homophonic period. This is something that is feasible with the PIC24FJxx sept.

The programm implments the summing tree algorithm. There are 5 variations: root, middle L, middle R, leaf L, leaf R. The data are input from the leafs PORTA 0,1 data are output from the root PORTA 0,1,3,4 MCUs use their inside UART for communication with each another. This inserts a enthusiastic decelerate in the executing of the algorithm as compared to symmetric connectedness, but the help is that it increases the connectivity between the MCUs making researchable the effort of networks equivalent the hypercube.

PIC24FJ16GA002 parallel processing computer PIC24FJ16GA002

The succeeding illustration shows the block plot of the comparable computer (line that the connectedness material is not shown as it is baculiform by the mortal!)

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